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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">CNTFRQ, Counter-timer Frequency</h1><p>The CNTFRQ characteristics are:</p><h2>Purpose</h2>
        <p>This register is provided so that software can discover the frequency of the system counter. The instance of the register in the CNTCTLBase frame must be programmed with this value as part of system initialization. The value of the register is not interpreted by hardware.</p>
      <h2>Configuration</h2><p>It is <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> whether CNTFRQ is implemented in the Core power domain or in the Debug power domain.
    </p>
        <p>For more information see <span class="xref">'Power and reset domains for the system level implementation of the Generic Timer'</span>.</p>
      <h2>Attributes</h2>
        <p>CNTFRQ is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="32"><a href="#fieldset_0-31_0">Clock frequency</a></td></tr></tbody></table><h4 id="fieldset_0-31_0">Bits [31:0]</h4><div class="field">
      <p>Clock frequency. Indicates the system counter clock frequency, in Hz.</p>
    <p>The reset behavior of this field is:</p><ul><li>On a Timer reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h2>Accessing CNTFRQ</h2>
        <p>CNTFRQ must be implemented as an RW register in the CNTCTLBase frame.</p>

      
        <p>In a system that recognizes two Security states, the instance of the register in the CNTCTLBase frame is only accessible by Secure accesses.</p>

      
        <p>CNTFRQ can be implemented as a RO register in any implemented CNTBaseN frame, and in the corresponding CNTEL0BaseN frame.</p>

      
        <p><span class="xref">'CNTCTLBase status and control fields for the CNTBaseN and CNTEL0BaseN frames'</span> describes the status fields that identify whether a CNTBaseN frame is implemented, and for an implemented frame:</p>

      
        <ul>
<li>Whether the CNTBaseN frame has virtual timer capability.
</li><li>Whether the corresponding CNTEL0BaseN frame is implemented.
</li><li>For an implementation that recognizes two Security states, whether the CNTBaseN frame, and any corresponding CNTEL0BaseN frame, is accessible by Non-secure accesses.
</li></ul>

      
        <p>For an implemented CNTBaseN frame:</p>

      
        <ul>
<li>CNTFRQ is accessible in that frame, as a RO register, if the value of <a href="ext-cntacrn.html">CNTACR&lt;n&gt;</a>.RFRQ is 1.
</li><li>Otherwise, the CNTFRQ address in that frame is RAZ/WI.
</li></ul>

      
        <p>For an implemented CNTEL0BaseN frame:</p>

      
        <ul>
<li>CNTFRQ is accessible as a RO register in that frame if both:<ul>
<li>CNTFRQ is accessible in the corresponding CNTBaseN frame.
</li><li>Either the value of <a href="ext-cntel0acr.html">CNTEL0ACR</a>.EL0VCTEN is 1 or the value of <a href="ext-cntel0acr.html">CNTEL0ACR</a>.EL0PCTEN is 1.
</li></ul>

</li><li>Otherwise, the CNTFRQ address in that frame is RAZ/WI.
</li></ul>
      <h4>CNTFRQ can be accessed through the memory-mapped interfaces:</h4><table class="info"><tr><th>Component</th><th>Frame</th><th>Offset</th><th>Instance</th></tr><tr><td>Timer</td><td>CNTBaseN</td><td><span class="hexnumber">0x010</span></td><td>CNTFRQ</td></tr></table><p>Accesses on this interface are <span class="access_level">RO</span>.</p><table class="info"><tr><th>Component</th><th>Frame</th><th>Offset</th><th>Instance</th></tr><tr><td>Timer</td><td>CNTEL0BaseN</td><td><span class="hexnumber">0x010</span></td><td>CNTFRQ</td></tr></table><p>Accesses on this interface are <span class="access_level">RO</span>.</p><table class="info"><tr><th>Component</th><th>Frame</th><th>Offset</th><th>Instance</th></tr><tr><td>Timer</td><td>CNTCTLBase</td><td><span class="hexnumber">0x000</span></td><td>CNTFRQ</td></tr></table><p>Accesses on this interface are <span class="access_level">RO</span>.</p><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:05; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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